schematic1 : page1

5
4
U1
33uF
C5
10uF
C6
1
100n 2
3
PGD 4
PGC 5
SDA 6
SCL 7
8
9
10
DDS_R 11
C12 DDSUD12
+3V3 13
10p
14
SDI
RA0
TL2
R3
DM
R4
10R
Boot
DP
C9 C10
10R
MCLR
+3V3
GND
PGD
PGC
USB-004B
22p 22p
1
2
3
4
5
J1
ProgPIC
Reset
+3V3
C7
28
100n
27
ADCCS
26
SCK
25
SDO
24
23
22 DM
21 DP
C8
20
1uF
19
PLLCS
18
PLLlock
17
DR
16
15 VBUS
C14
U2
10k
XT1
8MHz
R5
150R
C11
10p
D1
RED
MCLR
AVDD
AN0/C3INC/CTED1/RA0
AVss
AN1/CTED2/RA1
AN9/SCK2/RB15
PGED1/AN2/RB0
AN10/SCK1/RB14
PGEC1/AN3/RB1
AN11/RB13
AN4/SDA2/RB2
VUSB3V3
AN5/SCL2/RB3
PGEC2/RB11
Vss
PGED2/RB10
OSC1/CLKI/RA2
VCAP
OSC2/CLKO/RA3
Vss
SOSCI/RB4
SDA1/RB9
SOSCO/T1CK/RA4
SCL1/RB8
VDD
INT0/RB7
PGED3/RB5
VBUS
D
U3
24C512
1
2
3
4
A0
A1
A2
Gnd
VCC
PIC32MX250F128B
+3V3
R9
4k7
TL4
C17
C18 10uH
C19 C20 C21 C22
C23 C24 C25 C26
100n
1n
100n10p 100n10p
100n10p 100n10p
TL5
39nH
TL6
39nH
100n
R8
10k
1
2
3
4
5
6
7
8
Si2307
T1
C16
C15
shielding
TL3
100nH
1u
PLLlock
R16
150R
ADS1247
LD
PDBrf
DGND
DVdd
REFin
MUXout
SDgnd
SDVdd
C42
100n
C50
+3V3
D2
GRE
SCK
R21
SDO
1k
R23
PLLCS
1k
R25
100p
100p
U10
C58
47n
C60
47n
2
1
4Gin
R26
52R3
1
4
2
VPOS
VPOS
INHI
3
INLO
CLPF
VOUT
VSET
GND
TADJ
14
12
11
10
9
R24
C59
1k
TL9
100nH
125MHz
100n
4
VDD
OUT
3
B
C61
C62
100p
100p
1
EN
GND
2
C36
1n
R14
C37 1
1n
39R
R17
150R
C43 C44
2
J5
C80
1n
C82
1n
2
1
2G5_B
R41
52R3
R22
100n
C53 C54 C55
680R
2n2 470p39n
C56
Si2307
T2
C57
1n2
100n
C86
100p
C38
1n
+13dBm
8
7
6
5
RF2
GND
GND
RF1
CTLA
CTLB
RFC
VDD
HMC336
1
2
3
4
C40 C41
ERA-1
P/S
CLK
SERin
LE
GND
ATTin
VDD
PUP1
PUP2
SERout
GND
ATTout
18
17
16
15
14
13
C
C35
1n
max +10dBm
RFout
J2
1
R15
51R
HMC624
1n
1n
C45
C46
C47
C49
330p
330p
330p
330p
+13dBm
R19
10k
R27
39R
C63
1n
L2
68nH
C72
100n
1n
GND
INPA
OFSA
VPOS
OFSB
INPB
GND
AD8302
100nH
C68
15p
VCC
10uH
+3V3
C74
100p
MFLT
VMAG
MSET
VREF
PSET
VPHS
PFLT
14
13
12
11
10
9
8
R38
1k
R39
1k
C87
R32
51R
TL11
100nH
100nH
C69
15p
4
C65 1
1n
39R
C75
C76
C77
47p
100p
82p
R33
150R
R34
150R
B
Set atten. at prototype
U12
G
R29
In Out
G
C71
Set atten. at prototype
L4
IOUT
U13
1
2
3
4
5
6
7
1n
VCC
VCC
ERA-3
2
R31
0R
C30
100n
C64 FXO_HC536R
J4
C70
1n
C73
1n
C29
100n10p
C52
L3
R37
52R3
TL7
10uH
R28
360R
TL10
1
3
1
2
3
4
5
6
U8
U9
In Out
R18
150R
1n
2G5_A
L1
68nH
Set atten. at prototype
1k
U11
ADL5513
16
15
14
13
12
11
10
9
U6
ADF4351
1
2
3
4
5
6
7
8
100n
C51
J3
Vvco
RFoutBRFoutB+
RFoutARFoutA+
AGNDVCO
AVdd
AGND
C33
1n
4
25
26
27
28
29
30
31
32
C34
100n
100n10p
G
SCK
SDO
SDI
DR
ADCCS
RA0
20
19
18
17
16
15
14
13
12
11
U7
G
DVDD
SClk
DGND
Din
CLK
Dout/DRDY
RESET
DRDY
RefP0/GPIO
CS
RefN0/GPIO1 START
VrefOut
AVDD
VrefCom
AVSS
AIN0/IEXCAIN3/GPIO3
AIN1/IEXCAIN2/GPIO2
C48
R20
0R
SDA
SCL
D0
D1
D2
D3
D4
D5
24
23
22
21
20
19
18
17
1n
R13
51R
2
C39
C31 C32
R12
51R
Clk
Data
LE
CE
SW
Vp
CPout
CPgnd
+3V3
100n
R10
39R
C28
U5
1
2
3
4
5
6
7
8
9
10
C
TL8
10uH
100n
R7
1k
PCF8574
Vref
Vcom
Rset
AGNDVCO
Vtune
TEMP
AGNDVCO
Vvco
MCLR
R11
100R
16
15
14
13
12
11
10
9
A0 VCC
A1 SDA
A2 SCL
P0
INT
P1
P7
P2
P6
P3
P5
GND P4
100n
+3V3
C27
C13
R6
1k
U4
VCC
100n
AVDD
VCC
8
7
6
5
Vcc
WP
SCL
SDA
2
1uF
C4
TC1262
100n
24
23
22
21
20
19
1
2
3
4
D
VBUS
10n
CN1
C3
MCLR
10k
R2
ACG1
ACG2
ACG3
ACG4
ACG5
ACG6
C2
2
C1
+3V3
3
Vout
1
TL1
R1
Vin
2
7
8
9
10
11
12
1
GND
VCC
3
3
C66
1n
R30
39R
R35
150R
C67
1n
R36
150R
C78
100n
C79
C83
100n
R40
10k
1
2
3
4
5
6
R43
SCK
7
DDSUD
8
R44 100R
9
10
100R
11
12
13
R47 14
3k9
100n
100p
A
C81
C84
C85
100n
100n
100n
U14
D3
D2
D1
D0
DGND
DVDD
W_CLK
FQ_UD
CLKIN
AGND
AVDD
RSET
QoutB
Qout
D4
D5
D6
D7_SL
DGND
DVDD
Reset
Iout
IoutB
AGND
AVDD
DACBL
VINp
VINn
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R42
SDO
100R
DDS_R
IOUT
R45
51R
A
R46
51R
AD9851
Title
W obbler v.2.0 with phase detector
Size
A3
Date:
5
4
3
2
Document Number
19042015A01
Thursday, April 23, 2015
Rev
A
Sheet
1
1
of
1